Conventionally, a trench double diffused metal oxide silicon (Trench-DMOS) transistor is used to provide high power transistors for power integrated circuit applications. Various internal parasitic effects often impose design and performance limitations on conventional Trench-DMOS transistors. Conventional trench-gate DMOS with polysilicon gate equal to, below (Recessed-Gate Trench-DMOS) and above the silicon surface (PSU Poly-Stick-Up, or Stick-up poly gate, SUPG) requires a mask to either block the source N+ implant from the body contact region or form a “trench-contact” through which the exposed N+ Silicon may be etched to allow for a P+ implant to contact the body region of the DMOS transistor. Furthermore, standard trench-gate D-MOSFETs (or DMOS), with or without PSU (stick-up-poly or Poly-Stick-Up), require an alignment to form the Source contact, which can influence yield if there are misalignments or if the critical dimension (CD) control of the contact or other layers is not adequate (e.g., yield loss in the form of Igss gate-source leakage). A larger cell pitch would be required to accommodate the extra contact to gate alignment (and or CD control tolerances) which is undesirable since this would result in a power transistor with a larger on-resistance and a reduced efficiency. In addition, it is difficult to implement self-aligned contact.
U.S. Pat. No. 5,567,634 discloses metal oxide semiconductor (MOS) devices and a method of fabricating trench, double diffused MOS (DMOS) transistors with the contact to the transistor's source and body self-aligned to the trench. The self-aligned contact reduces the distance between trench edges with a resulting increase in packing density and current driving capability and decrease in on-resistance.
U.S. Pat. No. 5,684,319 discloses a DMOS device structure, and method of manufacturing the same features a self-aligned source and body contact structure which requires no additional masks. N+ polysilicon spacers are used to form the source region at the periphery of the gate polysilicon. However, the N+ polysilicon source only improves the source contact, which lowers the resistance, but it has no effect on body region. U.S. Pat. No. 5,665,619 disclose a trench DMOS transistor structure includes a contact to the transistor's source and body that is self-aligned to the trench and methods of fabricating the self-aligned contact structure. The methods rely on an oxide/nitride/oxide (ONO) stack on the active layer, and the use of an oxide etchback to protect the top of the Poly gate after poly gate etch back. Spacers are then used to protect the sidewalls. In addition, in these methods, an ONO stack may be used to protect the active region, and after the poly etch back, a thermal oxide is grown on the top of the poly gate.
U.S. Pat. No. 5,378,655 discloses a method of manufacturing a semiconductor device including an insulated gate field effect device in which the insulated gate is formed within a groove or recess. In this method, the oxide on top of the polysilicon gate is formed prior to forming the spacers.
U.S. Pat. No. 6,924,198 discloses a trench-gated MOSFET formed using a super self aligned (SSA) process that employs an insulating layer such as a glass layer and a contact mask to define contact openings for electrical connections to source regions of the MOSFET. A contact mask and an intervening glass are used in the otherwise self-aligned process to reduces coupling capacitance between source metal and the top of the embedded trench gate. A metal layer deposited to make electrical contact to source regions can be planarized, for example, ground flat using chemical-mechanical polishing to provide a flat surface to avoid formation of conductive traces that extend over the steps that the glass layer forms. However, a contact is used within the stripe and the body contact is not distributed.
Alpha & Omega Semiconductor of Sunnyvale, Calif., has disclosed trench MOSFETs having poly-stick-up (PSU) gate as shown in FIG. 1. An example of such a gate structure is described, e.g., in U.S. Patent Application Publication No. 20060071268, which is incorporated herein by reference. As shown in the perspective view illustrated in FIG. 1, a power MOSFET device 100 may include a drain 102 formed on a semiconductor substrate, a body 104, a source 106 that is embedded in the body and extends downward from the top surface of the body into the body. The device 100 also includes a gate 108 made of conductive material such as polycrystalline silicon (poly) that is disposed in a trench that extends through the source and the body to the drain. The top surface of the gate 108 extends substantially above the top surface of source 106. By extending the gate through the source, the gate overlaps the bottom of the source even when the source depth changes. A dielectric material layer 110 is disposed over the gate to insulate the gate from source-body contact. Appropriate dielectric material includes thermal oxide, low temperature oxide (LTO), boro-phospho-silicate glass (BPSG), etc. A metal layer (not shown) is disposed on the device to form contact with the source and the gate.
It would be desirable to develop a structure which achieves self-aligned source/body contact without using a mask, as well as a highly rugged and robust structure with low-resistance source and body contact. It would be further desirable to develop a structure which achieves low-thermal budget to realize shallow junctions, compatible with stripe and closed-cell geometries, compatible with standard foundry process, with standard metallization schemes to achieve low contact resistivity, compatible with ultra-small cell-pitch. It would be further desirable to produce a device with a low-cost of manufacture.
It is within this context that embodiments of the present invention arise.